Reduced error dividing circuit - uses two additional clock pulses to complete each subtraction cycle

摘要

The contents of the Divisor shift register (1) and Dividend register (2) are cycled through a 4 bit subtractor circuit (4). If the subtract cycle has a positive result - no remainder present - the first additional clock pulse adds a digit to the pulse counter (5). The second additional clock pulse is not used. Should the subtraction cycle have a regative result - a remainder present - the contents of the count register (5) are shifted into the Result register (7) by the first additional clock pulse. The second additional clock pulse resets the count register (5).