Variable length data processing apparatus for consecutively processing variable-length data responsive to one instruction

摘要

Data divided by delimiters representing the boundaries of the data is stored in a data memory. Instructions each including designation of a delimiter are stored in an instruction register. A control circuit decodes an instruction output from the instruction register, and repeats processing of the data read out from the data memory in accordance with the decoded instruction every time the data is read out therefrom. A delimiter detector outputs a coincidence signal when it detects that a delimiter which coincides with the delimiter in the instruction is present in the data read out from the data memory. When this coincidence signal is input to the control circuit, the control circuit ends the processing which has been performed in accordance with the instruction.