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Fast BCD/binary adder

机译:快速BCD /二进制加法器

摘要

A fast BCD/Binary Adder in which provision is made for selectively performing either binary or BCD arithmetic operations using an approach in which, for BCD addition, an appropriate correction value is always caused to be added to one of the input operands and an appropriate correction value conditionally subtracted from the result where required to give a proper BCD result. High speed operation is achieved by merging the binary input logic with the correction logic so as to provide for addition of the correction value concurrently with the addition of the input operands in a manner which automatically takes into account any inter-bit carries that may be produced by the correction value. In addition, provision is made for concurrently producing conditional sums (one assuming the presence of an input carry and the other assuming the absence of a carry) in parallel with the performance of look-ahead carry operations. An output logical selection circuit merges the selection logic for selecting the correct conditional sum (in response to the look- ahead carry produced) with the conditional subtraction logic required for BCD operation in a manner so that the two operations are performed concurrently during BCD operations.
机译:一种快速的BCD /二进制加法器,其中规定了使用一种方法进行选择性地执行二进制或BCD算术运算的方法,对于BCD加法,总是将适当的校正值添加到输入操作数之一并进行适当的校正如果需要给出适当的BCD结果,则从结果中有条件地减去该值。通过将二进制输入逻辑与校正逻辑合并在一起,从而以自动考虑可能产生的任何位间进位的方式,在与输入操作数相加的同时提供校正值的相加,即可实现高速操作通过校正值。此外,还提供了与先行进位进位操作并行执行的条件总和(一个假定存在输入进位,另一个假定不存在进位)。输出逻辑选择电路以某种方式将用于选择正确的条件和(响应于产生的前瞻进位)的选择逻辑与BCD操作所需的条件减法逻辑合并,以便在BCD操作期间同时执行两个操作。

著录项

  • 公开/公告号US5007010A

    专利类型

  • 公开/公告日1991-04-09

    原文格式PDF

  • 申请/专利权人 UNISYS CORP. (FORMERLY BURROUGHS CORP.);

    申请/专利号US19860844488

  • 发明设计人 LAURENCE P. FLORA;

    申请日1986-03-25

  • 分类号G06F7/50;

  • 国家 US

  • 入库时间 2022-08-22 05:46:37

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