Device and method for the generation of test vectors and testing method for integrated circuits

摘要

A device and a method are used to test integrated circuits, especially P.L.A.s. The possible faults of a circuit to be tested are determined including logic faults caused by the physical structure and relative position of the circuit elements in the integrated logic circuit. On the basis of the faults, a set of test vectors is determined, each fault modifying at least one of the test vectors applied to the circuit to be tested. It is possible to use test vectors which are modified by the greatest number of possible faults. By determining the test vectors on the basis of the faults which are to be detected, the tests can use a small number of vectors while, at the same time, there is certainty that it will be possible to detect all the faults in a given circuit. Advantageously, a hierarchically-organized set of cells is determined with certain cells consisting of small cells. The method and device can be used to test P.L.A.s by using a small number of test vectors, and are applicable to testing integrated circuits and P.L.A.s.