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Programmable logic array using internally generated dynamic logic signals as selection signals for controlling its functions
Programmable logic array using internally generated dynamic logic signals as selection signals for controlling its functions
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机译:使用内部生成的动态逻辑信号作为控制其功能的选择信号的可编程逻辑阵列
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摘要
The present invention provides an output logic macrocell for controlling configuration of an output for an integrated circuit wich provides a logic signal including a register responsive to a clock signal for latching the logic signal to provide a registered signal. An output selector receives both the logic signal and the registered signal and selects responsive to an output select signal, either the logic signal or the registered signal. A feedback path provides a feedback signal as data which is selected by a feedback selector responsive to a feedback select signal for selecting the logic signal or the registered signal as the feedback signal. Further, a clock signal enable circuit, responsive to a clock enable signal, enables or disables the clock signal to clock the register. Accordingly, the register, the output selector, the feedback path, and the clock enable circuit are all dynamically controllable by respective control signals.
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机译: 转换术语± Sup> [n i Sub>] f(+/-) min sup>的条件最小化结构的逻辑动态过程的方法Sub> AND ± Sup> [m i Sub>] f(+/-) min Sub>在功能添加结构中± Sup> f < Sub> 1 Sub>(Σ RU Sub>) min Sub>,不带纹波f 1 Sub>(± Sup>←←)和循环ΔtΣ Sub>→5∙f(&)-和5个条件逻辑函数f(&)-,并通过三元数系统的算术公理同时转换术语参数的过程f RU Sub>(+ 1,0,-1)及其实现其的功能结构(俄罗斯逻辑版本)