CDCFL logic circuits having shared loads

摘要

A CDCFL latch circuit having a plurality of inputs and first and second outputs includes a gate circuit responsive to logic input signals supplied to the plurality of inputs for providing complementary output logic signals at the first and second outputs when the gate circuit is rendered operative. A regeneration circuit is coupled to the first and second outputs for maintaining the complementary output logic signals at the first and second outputs when the regeneration circuit is rendered operative and the gate circuit is rendered non-operative. A shared load circuit provides current to the gate circuit when the gate circuit is operative and for providing current to the regeneration circuit when the regeneration circuit is operative. A control circuit responsive to a complementary clock signal and coupled between the shared load circuit and the gate and regeneration circuits alternately renders the gate circuit operative when the complementary clock signal is in a first logic state and the regeneration circuit operative when the complementary clock signal is in a second logic state.