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Method for reducing masking of errors when using a grid-based, 'cross- check' test structure
Method for reducing masking of errors when using a grid-based, 'cross- check' test structure
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机译:使用基于网格的“交叉检查”测试结构时减少错误掩盖的方法
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摘要
Several methods for reducing the occurrence of masking of errors when using "Cross-Check" integrated circuit testing arrays and data compression devices such as multiple input shift registers are disclosed. The methods reduce the probability that successive faults within the logic circuit nodes of the integrated circuit will cancel one another by insuring that signals from logically proximate circuit nodes are either not provided sequentially to the data compression circuitry or are provided in such a way as to store any given error in at least two different locations.
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