METHOD AND APPARATUS FOR HIGH-SPEED RESPONSE DIGITAL INTERFACE

摘要

PURPOSE: To improve a response time to a high interrupt frequency and a high resolution by dividing a digital value showing the read of a sensor, deciding a pulse width by the uppermost part and selectively changing a pulse at the lowermost part. CONSTITUTION: A bus 66 divides the digital value NP into NP 5 to 9 in the uppermost part and NW 0 to 4 in the lowermost part. Then, the uppermost part is transmitted to a counter 84. The counter 84 receives a system clock CK and a latch usable signal/LE. At this time, the counter 84 is previously set to the complement of the uppermost part of NP, and adds from this value up to the final count which is determined freely in change by a logic circuit of a CTRL-W signal on a lead wire 70. It is shown as the sequence of a pulse in which the duty cycle of each pulse at the uppermost part corresponds to the uppermost part, and a pulse width is decided. Then, since the lowermost part selectively changes its pulse, a response time is improved to a high interrupt frequency and a high resolution.