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SEQUENTIAL CIRCUIT AND FORMING METHOD THEREOF, CONTROLLER AND FINITE-STATE MACHINE

机译:时序电路及其形成方法,控制器和有限状态机

摘要

PURPOSE: To simulate all possible states (i.e., all possible combinations of pointers, buffers, etc.) of a model in a short time. CONSTITUTION: Conversion from a high level to a low level is constituted in the form of formal top-down development procedure based upon successive improvement. Staring with the high level (abstract) such as the formal abstraction, etc., of a standard protocol, successive improvement is done to generate a detailed model. The said improvement is performed so as to guarantee the establishment of properties, confirmed at a certain level of the abstraction, at all subsequent abstraction levels. The successive improvement ends at a low-level 'model' forming the final implementation of the protocol. On the basis of formal verification, implementation by the finite state machine of a control-oriented system is automatically performed in a short time.
机译:目的:在短时间内模拟模型的所有可能状态(即,指针,缓冲区等的所有可能组合)。构成:从高水平向低水平的转变是基于从上而下完善的正式自上而下的开发程序的形式。盯着标准协议的高级(抽象)等形式的抽象,进行了连续的改进以生成详细的模型。进行所述改进以便保证在所有后续抽象级别上都建立了在抽象的某个特定级别上确认的属性。后续的改进以构成协议最终实现的低级“模型”结束。在形式验证的基础上,由有限状态机实现的面向控制的系统会在短时间内自动执行。

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