Data packet converter for video telephone system - converts series of data words at one bit rate to series of data words at another bit rate using FIFO data and control buffers

摘要

The input circuit (1) accepts signals from a data line (2), clock signal line (3) and a cell synchronisation line (4). The input data are fed, via a FIFO data buffer (5), to the main control computer (7) and memory (9) and, via a FIFO control buffer (6), to a communications VME data bus interface (12). The video signal to the videophone is produced by the main control computer and memory and fed via an output interface (11) to the serial output line (11).