Frequency synthesizer having means for suppressing frequency instability caused by intermittent PLL operation

摘要

Frequency instability in a frequency synthesizer having a PLL circuit (3, 4, 5, 6, 7) operated intermittently to save its power consumption has been avoided by providing a means to suppress such instability. The instability has been found to be caused by phase uncertainty between reference frequency (fr) and output frequency (fout) at a time when the PLL is switched on. Therefore, a means (S2, S3) to equalize the phase of both frequencies has been provided. The new frequency synthesizer is stable enough for application to a mobile transmission system.