In a multiprocessor system having a plurality of processors connected through a bus, upon requesting message passing, a processor notifies, the request to other processors by designating identifiers of candidate destination processors from a register 5, an upper limit in a register UNR 8 and a lower limit in a register LNR 7. These provide a range for the number of destination processors required. A counter 9 counts acknowledge signals from candidate destination processors ready for message reception. A comparator 10 compares the count value with the lower and higher limit values in registers 7 and 8. If the count value is not less than the lower limit value, the sending processor determine that it can perform message passing. If the count value is treater than the upper limit value, the processor selects as many processors as the upper limit number from the candidate destination processors according to a rule based on priority, and then initiates the message passing to the processor thus selected.
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