The multiprocessor has duplicated redundancy built in to provide safe operation. A number of processors (RS1-RS6) have duplicated input/output units (E/A21, E/A22, etc.) that are led to two buses (B1, B2). A digital data from one processor (RS2) to another (RS1) is either transmitted in identical form or in true and inverted form by the I/O stages (E/A21, E/A22). Upon reception the data is subjected to a checking procedure. Any fault in the I/O unit is signalled back to the transmitting processor. Any further transmissions are switched to an alternative processor that has correctly operating I/O units.
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