Watch dog microprocessor operation monitoring circuit - with timing stage and reset circuit providing reset signal in response to received watch dog signal

摘要

The monitoring circuit has a timing stage (3) receiving a watchdog signal (WD) from the microprocessor (1), coupled to a reset circuit (7) providing a reset signal for the microprocessor. The output of the reset signal in response to the reception of the watchdog signal, is controlled via a time window pref. defined by the time constants of the first timing stage and a second timing stage, or a bistable multivibrator stage (28) between the first timing stage and the reset circuit. Pref. a number of reset signals can be supplied in response to an external clock pulse signal fed to the bistable multivibrator stage or to the reset circuit. ADVANTAGE - Reliable detection of error conditions.