Parallel data processing system with trap and stall control functions - has processor units controlled such that multiple instructions can be executed simultaneously

摘要

A parallel data processing system has 'N' processors that perform the simultaneous execution of M instructions. The instructions are transferred from memory (102) into an output unit (102) connections to arithmetic logic units (103,104), a floating point adder (105) and a floating point multiplier (106). The arithmetic logic units (ALU0,ALU1) connect to memory access control units (MA0,MA1) while the floating point units connect with test stages (EC1,EC2). Outputs are transferred to a multichannel data base unit. Operating with the unit is a trap register unit (130-133). ADVANTAGE - Has trap and stall control functions without reducing clock frequency.