Asynchronous transfer mode cell delay circuit for ISDN - multiplexes input signal cells with generated dummy cells to allow for propagation time through shift register

摘要

Dummy cells are produced at controllable intervals by a generator (1) whose output is multiplexed (3) with that of a first filter (2) extracting only cells requiring delay from the input signal. The multiplexed cells are delayed (4) in a shift register and forwarded to a second filter (5) which removes the dummy cells. This filter may be omitted if the generator (1) itself produces idle cells. The dummy cells allow delay to be implemented without interruption of duplex transmission. ADVANTAGE - Two-way data transmission is facilitated with different delays imposed on cells input in constant time intervals.