Multiple bit error detection and correction system employing a modified Reed-Solomon code incorporating address parity and catastrophic failure detection

摘要

An error detection and correction scheme is provided utilizing a modified Reed-Solomon code which has been optimized to detect erroneous memory location accessing and catastrophic failure condition of data containing either all ones or all zeros for N-bit wide semiconductor random access memories. When data is written to memory, the scheme calculates a series of check bits to represent a data word and the address of the location that the data word is to be stored and stores that information in memory. When data is read from memory, a series of syndromes are calculated based upon the data read and its memory location. These syndromes are compared which enables the system to detect which symbol of the data word an error occurs and the corrected value of that symbol.