Joint surveillance target attack radar system (JSTARS)

摘要

The central data processor of a radar system includes a plurality of Raytheon Company militarized VAX computer family model 860 super- minicomputers, each having a Raytheon Company MVCF-860 input/output expansion chassis and a Control Data corporation militarized disk system unit. A high speed, asynchronous, bidirectional communications channel provides a communications interface between a programmable signal processor and the super-minicomputers. A joint tactical information distibution system asynchronous, bidirectional communications channel interfaces a joint tactical information distribution system to the super- minicomputers. A plurality of militarized advanced disk system units and small computer systems interfaces of a digital display processor are interposed between one of the militarized advanced disk system units and the digital display processor. An operator work station local area network interfaces the digital display processor and the input/output expansion chassis of the central data processor.