Method and electrical circuit for eliminating time jitter caused by metastable conditions in asynchronous logic circuits

摘要

The present invention is a method and an electrical circuit (28 and 50) for effectively eliminating the effects of time jitter caused by metastable states by rejecting measurements made under timing conditions that could lead to the development of metastable states. In a preferred embodiment, the circuit of the invention effectively eliminates time jitter caused by metastable states in digital oscilloscope circuitry by determining in advance the timing conditions that can lead to such jitter and detecting whenever the transitions of trigger and trigger hold- off signals meet such timing conditions. The circuit then generates a "possible metastable" signal that can be used by the oscilloscope circuitry, or by the controlling software, to reject any measurement made under those timing conditions.