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Circuit arrangement for the routine testing of an interface between line terminator groups and the switching matrix network of a PCM telecommunication switching system
Circuit arrangement for the routine testing of an interface between line terminator groups and the switching matrix network of a PCM telecommunication switching system
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机译:常规测试线路终结器组和PCM电信交换系统的交换矩阵网络之间的接口的电路装置
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摘要
The interfaces between line terminator groups of a pair of redundant line terminator groups each comprise an interface circuit which makes it possible, by being equipped with a write-read memory, a switch- over device and a control device that controls these components, to test the interface parts belonging to an active line terminator group in a spot- check fashion during a time channel reserved for this purpose and to test the interface parts belonging to the passive line terminator group during all time channels on the basis of a respective check word mirroring.
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