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Instruction preprocessor for conditionally combining short memory instructions into virtual long instructions
Instruction preprocessor for conditionally combining short memory instructions into virtual long instructions
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机译:指令预处理器,用于有条件地将短存储指令组合为虚拟长指令
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摘要
An instruction memory apparatus for a data processing unit stores a sequence of instructions. At each instruction fetch cycle, two sequentially adjacent instructions are accessed. An instruction preprocessing unit, coupled to the internal instruction memory, combines the two sequentially adjacent instructions into a single long instruction word when the two instructions meet predefined criteria for being combined. The first of the two instructions is combined with a no- operation instruction to generate a long instruction word when the predefined criteria are not met. In that case, the second instruction [may be accessed again] is used during the next instruction fetch cycle as the first of the two sequentially adjacent instructions to be processed during that next instruction fetch cycle.
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