PURPOSE:To make the same detection as the detection when a sampling frequency is made long possible by obtaining the difference between the extracted output of the present time and the extracted output of the time N-times before the samling period in a subtraction circuit. CONSTITUTION:A binary counter 5 is synchronous counter which repeats counting by being inputted with clock pulses SCK. The count output DSC thereof is sampled and extracted in an extraction circuit 7 by the sampling pulse SLA formed from an input signal SFG in a pulse generating circuit 6. The output DER from the circuit 7 is inputted to the 1st delay circuit 8, the output from DERI from which is inputted to the 2nd delay circuit 9 of the next stage. The output therefrom is finally inputted to the N-circuit 10 of the N-th stage. The subtraction to subtract the output DERN of the circuit 10 and reference value D1 from the output DER of the circuit 7 is made in the subtraction circuit 11 and the subtracted output D0 is used as the discrimination output. The circuits 7-10 can be constituted of ordinary latching circuits. The extraction and delay of the input are executed by the latching operation with the pulse SLA.
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