Manner and delay optimization manner and logic design system of circuit component allocation

摘要

PURPOSE:To realize the delay optimization by allocating circuit elements taking into account the delay and driving force of packaging elements in the logic design system generating a real logic circuit consisting of packaging elements from the operation and function of circuits. CONSTITUTION:A circuit synthesizing means 12 converts the operation and function of the circuit inputted by an input means 11 into a logic circuit. A circuit element allocating means 13 allocates the logic gate in the logic circuit to the packaging elements stored in an element library 303, outputting the real logic circuit from an output means 14. In allocating the logic gate to the packaging element, the delay analysis is performed by means of a delay analysis means 15. As a result of a delay evaluation process 16, when the delay of the path to which the logic gate belongs is required to be shortened, elements with larger driving force are selected to be allocated in a driving force selecting process 17, performing the delay optimization.