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ARRAY BUILT-IN SELF TEST (ABIST)SYSTEM,BUILT-IN SELF TEST SYSTEM OF SEMICONDUCTOR CHIP AND METHOD OF TESTING MEMORY ARRAY
ARRAY BUILT-IN SELF TEST (ABIST)SYSTEM,BUILT-IN SELF TEST SYSTEM OF SEMICONDUCTOR CHIP AND METHOD OF TESTING MEMORY ARRAY
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机译:阵列内置自测(abist)系统,半导体芯片内置自测系统和存储器阵列测试方法
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摘要
PURPOSE: To provide an array built-in self test(ABIST) system improved for a semiconductor chip. CONSTITUTION: An array is tested along one direction for discriminating a defect cell of each column, and a column address having the defect cell is stored in a first register 16. The array is tested further along a row or the column for discriminating an additional defect cell while masking the cell having the stored column address. Row addresses having the defect cells are stored in a second register 20 until all second registers 20 store the row addresses. The array is continued to be tested along the row or the column after the row addresses are stored, and the cells having the stored column or row addresses are masked. The column addresses of remaining additional defect cells are stored in the unused register of the first register 16.
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