LOGICAL SIMULATION-ONLY PROCESSOR HAVING MEMORY SIMULATION MECHANISM

摘要

PURPOSE:To realize evaluation of a logic circuit in a state here an evaluation subject memory and an evaluation subject gate coexist, by using an internal state holding memory for an evaluation subject memory and a net status memory for an address signal. CONSTITUTION:An exclusive processor PC.9-p transfers data to a PC.9-q via a processor communication means 7. An event produced at a time point (t) and related to an unit (g) of a section constitution 8-p is held 2 and then read out precedingly to a fan-out pipeline 4 at the point (t) in terms of the input change unit (g) set at a time point (t+1). When plural inputs change simultane ously, the information is held 6 while deleting the overlap information. At the same time, the net status information corresponding to both input and output values are held by a memory 1 and the change information is sent to the means 7 and a buffer 2. Then an evaluation subject memory is divided into cells and set in response to a 4-input/1-output evaluation gate. An internal state holding memory 10 for an evaluation subject memory and a net status memory 1 for an address signal are provided for evaluation of an evaluation subject gate and an evaluation subject memory forming a logical unit respectively.