PURPOSE: To increase the operation speed of the mathematical logical operation unit (ALU) in arithmetic mode wherein a carry-out signal of addition, multiplication, etc., is generated by separating a latch clock which is supplied to a latch circuit into a low-order bit side and a high-order bit side. ;CONSTITUTION: The ALU enters an arithmetic mode of addition, multiplication, subtraction, AND, OR, or comparison selectively according to an instruction that a CPU sends, and processes data inputted from bus lines BUS0-BUSn through latch circuits Lat.0-Lat.n. This unit is equipped with 1st and 2nd buffers Buff.1 and Buff.2 and then performs the load separation of the latch clock Φconsisting of low-order bits 0-(m) and high-order bits (m+1)-(n) to reduce the load on the low-order bits 0-(m). Consequently, when this is applied to, for example, 32-bit width ALU, the rising of a latch clock Φ consisting of about four low-order bits can be made high speed.;COPYRIGHT: (C)1993,JPO&Japio
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