Clock control system and method for a parallel variable speed constant frequency power system

摘要

A clock control system for a multiple channel electric power system includes a master clock circuit (28) and control circuitry (40) in each parallel connected channel. The channel control circuits are initially phase-locked to a master clock signal. If the master clock signal is out of a preselected frequency range, the individual channel control circuits (38, 40) are decoupled from the master clock signal and one of those circuits produces a backup clock signal. The control circuits in the remaining channels are then phase-locked with the backup clock signal to provide continued parallel system operation.