INTERFACE CIRCUIT OF COMMON RAM BETWEEN MAIN CPU AND SUB-CPU

摘要

The X,Y communication data and ordinary data are stored on a same area of a common RAM to minimize logic circuit. An interrupt signal is transmitted to a sub CPU when a main CPU accesses a common RAM so that X,Y communication data access delay time due to common usage of a common RAM is shortened. The circuit includes an interrupt signal generator (12) comprising a flip-flop (F/F1) and inverters (I1,I2) to generate and to transmit interrupt signal to a sub-CPU when a write enable signal is generated by a main CPU, a handshake interface unit (13) for applying output signal of access control port (P1) of a sub-CPU to a control data port (D7) of a main CPU according to read enable signal of a main CPU.