首页> 外国专利> A method and a cache memory controller for fetching data against a central processing unit (CPU) to further reduce CPU idle time

A method and a cache memory controller for fetching data against a central processing unit (CPU) to further reduce CPU idle time

机译:用于针对中央处理单元(CPU)获取数据以进一步减少CPU空闲时间的方法和高速缓冲存储器控制器

摘要

A method and cache memory controller for fetching data against a CPU to further reduce CPU idle time are disclosed.;Although the cache memory initiated by the conventional cache miss is still in progress and the data word is stored in a memory location corresponding to the memory block offset of the memory block frame to which the data word is mapped, Fetch data from the cache-main memory layer to return to the CPU.;As a result, the CPU idle time due to the cache read miss is further reduced.
机译:公开了一种用于针对CPU获取数据以进一步减少CPU空闲时间的方法和高速缓冲存储器控制器。尽管由传统高速缓存未命中启动的高速缓冲存储器仍在进行中,并且数据字被存储在与该存储器相对应的存储器位置中数据字映射到的存储块帧的块偏移量,从缓存主存储层获取数据以返回到CPU。结果,由于缓存读取未命中而导致的CPU空闲时间进一步减少。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号