首页> 外国专利> Built-in test circuitry and speed test methods that provide simple and accurate AC testing of digital microcircuits using low-bandwidth test equipment and probe stations

Built-in test circuitry and speed test methods that provide simple and accurate AC testing of digital microcircuits using low-bandwidth test equipment and probe stations

机译:内置测试电路和速度测试方法,可使用低带宽测试设备和探针台对数字微电路进行简单而准确的交流测试

摘要

The invention relates to a method and system for transferring data between an integrated circuit (ATE) and an integrated circuit in accordance with a low-speed clock, which may have an arbitrarily long period, Circuit and technique for operating a storage element in an integrated circuit in accordance with a high-speed clock having the same. In one embodiment, the input latches at the inputs of the integrated circuit receive the test data from the ATE, and the output latches at the outputs provide the test result data to the ATE. According to an alternating single cycle of the low speed clock and the high speed clock, the delay through the combinational network between the data transmission paths between the input latch and the output latch is checked according to the high speed clock. In another embodiment, the test data is serially scanned into a scan register in accordance with a series of slow clock cycles. After the scan data is scanned, the scan registers are operated in parallel to check the delay of the combinational network between them.
机译:本发明涉及用于根据可以具有任意长的周期的低速时钟在集成电路(ATE)和集成电路之间传送数据的方法和系统,用于操作集成电路中的存储元件的电路和技术电路根据具有它的高速时钟。在一个实施例中,集成电路的输入处的输入锁存器从ATE接收测试数据,并且输出处的输出锁存器将测试结果数据提供给ATE。根据低速时钟和高速时钟的交替单周期,根据高速时钟检查通过输入锁存器和输出锁存器之间的数据传输路径之间的组合网络的延迟。在另一个实施例中,根据一系列慢时钟周期,将测试数据串行扫描到扫描寄存器中。在扫描数据被扫描之后,扫描寄存器并行运行以检查它们之间组合网络的延迟。

著录项

  • 公开/公告号KR930011489A

    专利类型

  • 公开/公告日1993-06-24

    原文格式PDF

  • 申请/专利权人 완다 케이. 덴슨-로우;

    申请/专利号KR19920022564

  • 发明设计人 윌리엄 디. 파웰;

    申请日1992-11-27

  • 分类号H04L1/00;

  • 国家 KR

  • 入库时间 2022-08-22 05:04:14

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