Tetrode circuit, e.g. for HF power amplifier - comprises two FET(s) forming tetrode with signal input and control input, two potential dividers and third FET for automatic gain control

摘要

The circuit comprises a two-FET (T1,T2) tetrode whose input (1) is connected to the gate (G1) of the first FET (T1). A control voltage input (2) connects to the gate (G2) of the second FET (T2). The quiescent point of the tetrode is determined by resistances (R1-R5) and a third FET (T3). A potential divider (ST1) is connected to the gate of the second FET, and a second potential divider (ST2) is connected to the gate of the third FET. The gate of the first FET is connected to the source and gate of the third FET via a resistance (R5). The two potential dividers are connected at a common end to ground and the first has its other end connected to the control voltage input. ADVANTAGE - Allows operating point of tetrode to be set without using additional external pins, and without dynamic losses.