Delay time calculator for logic block contg. MOS transistor - uses layout memory and stores delay times according to input signal gradient for each layout

摘要

A method of computing a delay time in transferring a signal from an input to an output section of a logic block contg. a MOS transistor involves using a device (12) which stores the lay-out of the fun tion block. The delay times of different functional blocks are stored (14) according to inut signal gradient. The input signal gradient is derived from the lay-out and the corresponding delay parameter is delivered. The output impedance of the block is derived (15) from the capacitance of a concentrated RC constant and the delay parameter value. The delay time is derived (16) from the capacitance and delay parameter values. USE/ADVANTAGE - Delay time determined at very great accuracy under all conditions without increasing memory requirements.