Error detection facility for multi processor system - has each processing module based upon two processors operating with delay and error determined by comparison of output

摘要

The multi processor system has identical processor modules (1.1-1.3) coupled onto a system bus (4) together with a common memory (2) and I/O module (3). A serial bus (7) is used for the transmission of error information. Within the processor modules is a start circuit (30) controlling the delay between a pair of processor units (10a, 10b). The processors connect with a comparator (31) that operates with error watchdog circuit (32) and a sub processor (33) for status control. Error conditions are indicated when the processing operations for the two processor units are not complete within a specific period. ADVANTAGE - Requires little hardware for error detection.