INSERTING DEBUG INSTRUCTIONS INTO A CPU WITH ON-CHIP INSTRUCTION CACHE.

摘要

A structure and a method for 'jamming' instructions into a CPU core in a microprocessor with an on-chip cache memory. In one embodiment, the microprocessor provides a debug mode, which is activated by a signal on a mode pin. In the debug mode, when a signal is received on a second mode pin, a cache miss is generated at the next instruction fetch. Thus, the processor is forced to fetch the next instruction from main memory. The external testing device then provides the instruction on the memory bus as though it is fetched from the main memory in response to the read cycle resulting from the cache miss. Thus the contents of the cache are preserved to maintain consistency before and after interruption of the instruction stream. IMAGE