MOS decoder circuit implemented using a neural network architecture

摘要

A decoder circuit based on the concept of a neural network architecture has a unique configuration using a connection structure having CMOS inverters, and PMOS and NMOS bias and synapse transistors. The decoder circuit consists of M parallel inverter input circuit corresponding to an M-bit digital signal and forming an input neuron group, a 2.sup.M parallel inverter output circuit corresponding to 2.sup. M decoded outputs and forming an output neuron group, and a synapse group connected between the input neuron group and the output neuron group responsive to a bias group and the M-bit digital original for providing a decoded output signal to one of the 2.sup.M outputs of the output neuron group when a match is detected. Hence, only one of the 2.sup.M outputs will be active at any one time.