Address selection circuit including address counters for performing address selection

摘要

An n-bit address selecting instruction read from a program ROM encludes a control bit part and an nm-bit (m n) operand part. Data used for address selection is stored in k (km) extra bit positions of the control bit part. The data stored in the control bit part is supplied to a control bit data detecting circuit. The detecting circuit is responsive to the control bit data in the control bit part to produce first and second control signals. Detecting an address selecting instruction, the detecting circuit produces the first control signal so that a first data entry gate is enabled. When the first data entry gate is enabled, address selecting data stored in the operand part included in the address selecting instruction is written into an m-bit address counter. When the detecting circuit detects the address selecting instruction and that the number of bits of an address to be selected is "m+1" bits or more, the second control signal enables a second data entry gate. As a result, part of data in the control bit part is written into a k-bit address counter as address selecting data. The "m+k"-bit address selecting data is output from the m-bit address counter and the k-bit address counter. The bits of the address output are supplied to the program ROM simultaneously.