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deijitsuto line balance level revision method

机译:deijitsuto线余额水平修改方法

摘要

PURPOSE:To balance a sense margin, and also, to prevent a digit line from receiving noise of other digit lines by short-circuiting a pair of digit lines at the time of precharge, and also, connecting an external capacity. CONSTITUTION:A precharge signal phiP1 becomes L, a word line WL rises and a sense operation starts, and H or L of a digit line is decided. In this active period, a reset signal phiP2 becomes H, and the level of a nodal point N21 is pulled down. Subsequently, when a precharge operation is started, the signal phiP2 and the word line WL fall, and thereafter, the signal phiP1 becomes H. As a result, the digit lines DL, the inverse of DL are short-circuited by a transistor TR Q21, and by capacity division, the levels of the lines DL, the inverse of DL become 1/2VCC theoretically. Simultaneously, the lines DL, the inverse of DL are connected to an external capacity C21 by TRs Q22, Q23, and since the capacity division to this capacity C21 is also added, the level of the lines DL, the inverse of DL drops down a little from exact 1/2VCC, and becomes a corrected 1/2VCC level. Also, said line does not become a noise source.
机译:目的:通过预充电时使一对数字线短路,并连接外部电容,以平衡感测裕度,并防止数字线接收其他数字线的噪声。组成:预充电信号phiP1变为L,字线WL上升,并且读出操作开始,并确定数字线的H或L。在该有效时段中,复位信号phiP2变为H,并且节点N21的电平被下拉。随后,当预充电操作开始时,信号phiP2和字线WL下降,其后,信号phiP1变为H。结果,数字线DL,DL的反相被晶体管TR Q21短路。 ,并且通过容量划分,线路DL的电平(DL的反相值)在理论上变为1 / 2VCC。同时,线路DL(DL的倒数)通过TR Q22,Q23连接到外部电容C21,并且由于还对该电容C21进行了容量划分,因此线路DL(DL的倒数)的电平下降了a与精确的1 / 2VCC差值很小,并变为校正后的1 / 2VCC电平。而且,所述线路不会成为噪声源。

著录项

  • 公开/公告号JPH0634355B2

    专利类型

  • 公开/公告日1994-05-02

    原文格式PDF

  • 申请/专利权人 NIPPON ELECTRIC CO;

    申请/专利号JP19870016515

  • 发明设计人 MORITA YASUSHIGE;

    申请日1987-01-26

  • 分类号G11C11/409;

  • 国家 JP

  • 入库时间 2022-08-22 04:53:26

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