首页> 外国专利> FAST ALGORITHM DISCRETE COSINE TRANSFORMER/INVERSE TRANSFORMER

FAST ALGORITHM DISCRETE COSINE TRANSFORMER/INVERSE TRANSFORMER

机译:快速算法离散余弦变换/逆变换

摘要

PURPOSE: To accelerate processing speed by decreasing the number of times of computation by constituting discrete cosine transform/in-verse discrete cosine transform by using a fast algorithm signal flow graph. ;CONSTITUTION: A four-point fundamental arithmetic unit is equipped with a selector 31 which selects transform coefficients K1-K8 and a selector 32 which selects input signals A, B, C, and D. A selected transform coefficient is multiplied by the input signal by a multiplier 33. and the output of the multiplier 33 is added on that of a selector 37 by an adder 34, and an addition result is stored transiently in data storing registers 35, 36. Data stored in the data storage registers 35, 36 are selected by the selector 37, and are fed back to the adder 34. Final transform data Is stored in registers 38-41. In such a way, since a circuit can be configured by one multiplier 33 and adder 34, a circuit scale can be compressed, and also, operating speed can be guaranteed.;COPYRIGHT: (C)1994,JPO&Japio
机译:目的:通过使用快速算法信号流图构成离散余弦变换/逆离散余弦变换来减少计算次数,从而加快处理速度。 ;组成:四点基本算术单元,具有选择器31和选择器32,选择器31选择转换系数K1-K8,选择器32选择输入信号A,B,C和D。选择的转换系数与输入信号相乘。通过乘法器33将乘法器33的输出与选择器37的输出相加。将相加结果暂时存储在数据存储寄存器35、36中。将数据存储在数据存储寄存器35、36中选择器37选择“ 1”,并将其反馈到加法器34。最终变换数据存储在寄存器38-41中。这样,由于电路可以由一个乘法器33和加法器34构成,因此可以压缩电路规模,并且还可以保证工作速度。;版权所有:(C)1994,JPO&Japio

著录项

  • 公开/公告号JPH06195369A

    专利类型

  • 公开/公告日1994-07-15

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP19920357439

  • 发明设计人 SON GETSUEI;KAWAKATSU YASUHIRO;

    申请日1992-12-24

  • 分类号G06F15/332;G06F15/66;H03M7/30;H04N1/415;H04N7/133;

  • 国家 JP

  • 入库时间 2022-08-22 04:52:54

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