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PLL-FM DEMODULATOR

机译:PLL-FM解调器

摘要

PURPOSE: To obtain high sensitivity by making a loop band width of a PLL broad in the PLL-FM demodulator. ;CONSTITUTION: An FM signal e1(t) and a signal e4(t) from a VCO (voltage controlled oscillator) 7 are synchronizingly detected by a synchronization detector 9 in the state of in-phase, then outputs e6(t) and e4(t) are mixed by a mixer circuit 11, a signal e1(t) and the obtained signal e7(t) are calculated by a computing element 13 to obtain a noise component e8(t). The signal e8(t) is fed back to the computing element 3 at a pre-stage of the PLL loop and subtracted by the e1(t) and the difference is fed to a phase comparator 4.;COPYRIGHT: (C)1994,JPO&Japio
机译:目的:通过在PLL-FM解调器中使PLL的环路带宽变宽来获得高灵敏度。 ;构成:由同步检测器9同步检测FM信号e 1 (t)和来自VCO(压控振荡器)7的信号e 4 (t)在同相状态下,输出e 6 (t)和e 4 (t)被混频器电路11混频,信号e 1通过计算元件13计算(t)和获得的信号e 7 (t),以获得噪声分量e 8 (t)。信号e 8 (t)在PLL环路的前级反馈到计算元件3,并减去e 1 (t)和差送入相位比较器4。版权:(C)1994,JPO&Japio

著录项

  • 公开/公告号JPH0677818A

    专利类型

  • 公开/公告日1994-03-18

    原文格式PDF

  • 申请/专利权人 CLARION CO LTD;

    申请/专利号JP19920248797

  • 发明设计人 FUKUOKA NOBUHIRO;AMASAWA KIYOSHI;

    申请日1992-08-25

  • 分类号H03L7/08;H03D3/02;H04S3/00;

  • 国家 JP

  • 入库时间 2022-08-22 04:50:03

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