METHOD AND MECHANISM FOR TESTING ARRAY EMBEDDED IN MICROPROCESSOR, AND COMPARISON-COMPRESSION REGISTER ARRANGED IN SYSTEM FOR TESTING ARRAY

摘要

PURPOSE: To provide the mechanism and method for testing a known error place in an embedded array with a series of predetermined test patterns. ;CONSTITUTION: The said mechanism includes a determinative test pattern generator 14 which sends a test pattern to the array 12. The pattern is previously selected according to the fault trend of the array 12. The contents of the array 12 are read out and compared with the test pattern to generate a current error term. The current error term is compressed by a register 16 through logical operation and it saves an error display. The contents of the register 12 constitute a cumulative error term and can be read out to judge whether an error occurs or not. Respective columns of the tested array 12 correspond to bit positions in the cumulative error term and a user can judge which column in the array 12 causes the error.;COPYRIGHT: (C)1994,JPO