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PDM ACCUMULATOR SECONDARY LOOP FILTER CONVERTING MULTI-BIT PHASE ERROR INPUT TO FORWARD/DELAY CONTROL FOR STEPWISE CLOCK GENERATOR
PDM ACCUMULATOR SECONDARY LOOP FILTER CONVERTING MULTI-BIT PHASE ERROR INPUT TO FORWARD/DELAY CONTROL FOR STEPWISE CLOCK GENERATOR
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机译:PDM累加器次级环路滤波器将多位相位误差输入转换为步进时钟发生器的正向/延迟控制
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摘要
PURPOSE: To convert a multi-bit phase error input signal, with respect to a phase locked loop, into a high resolution control signal for a polyphase clock generator that supplies a sample clock output signal with a sample clock cycle period. ;CONSTITUTION: In a pulse density modulation(PDM) accumulator secondary loop filter, a phase error signal is given to a proportional accumulator 102, in which a phase error term proportional to a phase error input signal is obtained and it is fed to both an integration device accumulator 108 and an integration + proportion adder circuit 110. Then an integration + proportional output term is fed to a PDM accumulator 120. The PDM accumulator 120 interfaces the integration + proportion term to a polyphase clock generator. An adder 122 stores the integration + proportion term. Every time an overflow or underflow takes place in the adder 122, the polyphase clock generator jumps one phase period via a shift/idle signal PJEN.;COPYRIGHT: (C)1994,JPO
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