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RECEPTION INPUT ELECTRIC FIELD STRENGTH DETECTION CIRCUIT
RECEPTION INPUT ELECTRIC FIELD STRENGTH DETECTION CIRCUIT
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机译:接收输入电场强度检测电路
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摘要
PURPOSE: To detect accurately an electric field strength by sampling a prescribed level (symbol point) of a received wave when the electric field strength of a received digital modulation wave such as a π/4 shift QPSK modulation wave whose instantaneous level is fluctuated is detected. ;CONSTITUTION: The detection circuit is provided with a logarithmic amplifier 1 receiving a digital modulation wave 101 whose instantaneous level is fluctuated and outputting a DC voltage 102 corresponding to its electric field strength, an A/D converter 2 receiving the DC voltage 102 and outputting a converted digital quantity 103, a clock recovery circuit 3 recovering a recovered clock 104 from the digital modulation wave 101 and a clock synchronization circuit 4 receiving the recovered clock 104, synchronizing it and outputting a sampling clock 105 having a timing coincident with a symbol point of the digital modulation wave 101, and the sampling clock 105 is used for the sampling timing of the A/D converter 2 so as to sample the symbol point where the level of the received digital modulation wave 101 is constant.;COPYRIGHT: (C)1994,JPO&Japio
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机译:目的:当检测到接收到的数字调制波(例如π/ 4位移QPSK调制波)的瞬时电平发生波动时,通过对接收波的规定电平(符号点)进行采样来准确检测电场强度。组成:检测电路具有对数放大器1,其接收瞬时电平波动的数字调制波101,并输出与其电场强度相对应的DC电压102; A / D转换器2,接收DC电压102,并输出转换后的数字量103,时钟恢复电路3从数字调制波101中恢复恢复的时钟104,时钟同步电路4接收恢复的时钟104,使其同步并输出定时与符号点一致的采样时钟105采样时钟105用于A / D转换器2的采样时序,以采样接收到的数字调制波101的电平恒定的符号点。 )1994,日本特许厅
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