SHARED ACCESS OF A CENTRAL DATA PROCESSOR AND A DECENTRALIZED INPUT PROCESSOR TO A COMMON STORAGE.

摘要

The invention relates to a method for controlling a digital communication system having a central data processor and several decentralised input/output processors controlling peripheral devices, the decentralised input/output processors in each case exhibiting multiple-access memories and their own interface device for internal information transmission with the central data processor and the central data processor accessing the peripheral devices in interleaved manner during faultless operation and with the access of the central data processor to the multiple-access memory of in each case a particular input/output processor, the latter being switched into the hold state for a time corresponding to the maximum occupation time of the central data processor. The central data processor (DP) places the decentralised input/output processor (IOP) into the hold state. The peripheral program requests occurring during this process are stored in the multiple-access memory (DPR) and are subsequently sequentially processed by the timing device (ZE) of the input/output processor (IOP) after the central data processor (DP) has been blocked. Such a method is used for controlling digital communication systems in which a central data processor and decentralised input/output processors have shared access to one memory. IMAGE