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RADIX-16 DIVIDER USING OVERLAPPED QUOTIENT BIT SELECTION AND CONCURRENT QUOTIENT ROUNDING AND CORRECTION

机译:RADIX-16除法器,使用重叠的位选择和并发的环绕和校正

摘要

RADIX-16 DIVIDER USINGOVERLAPPED QUOTIENT BIT SELECTIONAND CONCURRENT QUOTIENT ROUNDING AND CORRECTIONABSTRACTA radix-16 divider, generally comprising two improvedradix-4 dividers cascaded combinatorially, also utilizesimproved overlapping quotient bit selection, together withconcurrent quotient bit selection and rounding techniques,to produce four bits of quotient per divider cycle withreduced hardware requirements.
机译:RADIX-16除法器的使用重叠的商位选择以及当前的商号环绕和更正抽象一个基数为16的除法器,通常包括两个改进的radix-4分频器组合级联,也利用改进了重叠商位选择,以及并发商位选择和舍入技术,每个除法器周期产生四位商降低了硬件要求。

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