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Cache memory coherency control provided with a read in progress indicating memory
Cache memory coherency control provided with a read in progress indicating memory
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机译:高速缓存一致性控制,带有正在进行的读取指示内存
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摘要
A cache memory subsystem couples to main memory through interface circuits via a system bus in common with a plurality of central processing subsystems which have similar interface circuits. The cache memory subsystem includes multilevel directory memory and buffer memory pipeline stages shareable by at least a pair of processing units. A read in process (RIP) memory associated with the buffer memory stage is set to a predeterind state in response to each read request which produces a miss condition to identify the buffer memory location of a specific level in the buffer memory which has been preallocated. The contents of the buffer memory stage are maintained coherent with main memory by updating its contents in response to write requests applied to the system bus by other subsystems. Upon detecting the receipt of data prior to the receipt of the requested data which would make the buffer memory contents incoherent, the cache switches the state of control means associated with the RIP memory. Upon receipt of the requested data, the directory memory is accessed, the RIP memory is reset and the latest data is forwarded to the requesting processing unit as a function of the state of the control means.
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