A broadband switching array for equalizing the delay experienced by input signals as they propagate through their respective switching paths, and for providing output signals having uniform logical polarities. A cascaded set of delay means (SXX) is connected to each of the input ports of the array in accordance with the amount of additional delay that is needed to accomplish equalization. Likewise, a cascaded set of inverter means (30) is connected to each output port so that each switching path performs a common number of inversion operations, thereby allowing the output signals to have the same logical polarity.
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