Feedback amplifier for regulating cascode gain enhancement

摘要

A regulated cascode circuit with enhanced gain includes a cascode section including a common source MOS transistor (m₁) of a first polarity and a cascode device (m₂) wherein the drain of the common-source MOS transistor (m₁) is coupled to the source of the cascode device. An input to the regulated cascode circuit is applied to the common source MOS transistor (m₁) and an output of the regulated cascode circuit is developed at the drain of the cascode device (m₂) across both the common source MOS transistor (m₁) and cascode (m₂) device. A feedback amplifier circuit (10) has its input (12) connected to the drain of the common source MOS transistor (m₁) and its output (20) connected to a gate of the cascode device (m₂) for driving the cascode device (m₂). The feedback amplifier (10) includes a source follower MOS transistor (m₈) of a second polarity opposite the polarity of the common source MOS transistor (m₁) for sensing voltage developed at the drain of the common-source MOS transistor (m₁). A common gate MOS transistor (m₉) of the first polarity has its source coupled to a source of the source follower MOS transistor (m₈), and a steering device coupled (m₅ and m₆) to the drain of the common gate MOS transistor (m₉) for steering current developed in the source follower MOS transistor (m₈) and common gate MOS transistor (m₉) combination to a load device (m₇). The load device (m₇) is coupled to current steering device (m₅ and m₆) for developing a voltage to be supplied to the output of the feedback amplifier (10) and to the gate of the cascode device (m₂). The drain of the common source MOS transistor (m₁) is clamped to a desired voltage thus providing maximum voltage swing for small signal voltage at the output of the regulated cascode circuit while keeping the common source MOS transistor and cascode device (m₁ and m₂) in the high gain saturation region. The feedback amplifier (10) also receives a bias voltage from a separate bias circuit (Fig. 7) to establish the desired voltage at the drain of the common source MOS transistor (m₁) wherein the bias voltage is supplied to the gate of the common gate MOS transistor (m₉).