Multiplier for digital filter using square ROM and finite impulse response (FIR) digital filter including it

摘要

The multiplier for multiplying the input data X (n) by the coefficient C comprises a first adder for adding the input data X (n) and the coefficient C, a second adder for adding the input data X (n) (n) + C, X (n)-C) of the first and second adders, respectively, and a second adder for adding the sign inverted value C of the coefficient C to the outputs X (n) + C | and | X (n)-C |, respectively, and outputting the output values of the first and second absolute value circuits as data, By value First and second storage means which are stored in the storage means, The output of the second storage means And a third adder for adding the sign inverted value, so that the structure is simple and high-speed multiplication processing is possible.