Parallel Cyclic Redundancy Check (CRC) Code Generation Circuit for Asynchronous Transfer Mode (ATM) Cell Header Error Control (HEC) Code Generation

摘要

The present invention relates to a parallel CRC code generation circuit for generating an HEC code of an asynchronous transfer mode (ATM) cell header, and more particularly to a parallel CRC code generation circuit for receiving a clear signal (CLR) (A0 to A7) for transmitting the information of one octet in parallel; a line memory (A0 to A7) for transmitting the information of one octet in parallel; An input unit for inputting one octet of information transmitted from the line means and one octet of data from the data storage means, (37) for sequentially performing CRC generation polynomial operation by one octet using data of one octet and data of the data storage means (6) end A CRC control signal transmission line (CRC ENA) for inputting a CRC control signal to be input to the CRC circuit; and a control unit connected to the calculation unit and the CRC control signal transmission line, And a 1 octet parallel output line (B0 to B7) connected to the data storage means (6). The data storage means (6)