FIFO with data expansion-compression in binary steps - uses shifted counter outputs to control address generators for read=write

摘要

The FIFO (30) contains a memory matrix (12), read and write clock counters (16,13), read and write address decoders (18,14), write register (15) clocked by a write clock (WK2), and a sense amplifier/buffer (19) clocked by a read clock (RK2). The FIFO implements data reduction in binary steps for example a reduction of 1/2 reads alternate data bits into the memory: '00011011' is input as '0011'. The scaling is implemented by connecting write counter outputs appropriately to the write address generator. For data expansion, data are repeated for 2,4,8 clock periods etc. The connection of the read counter (16) outputs (Q1,Q2,Q3) to the address decoder (18) (A0,A1,A2) implements an expansion factor of 2. ADVANTAGE - Data reduction/expansion by simple circuit addition to FIFO circuit.